In via technology, a skip via can be formed through many insulator layers, e.g., bypassing one or more wiring structures within the insulator layers, to connect with a lower wiring structure. This provides improved resistance characteristics, minimizes capacitance for a lower wiring structure, e.g., at M0 layer, as well as provides area efficiencies in the chip manufacturing process.
There are many challenges to using skip vias. For example, in the manufacturing process, the skip via will need to land on a wiring structure in a lower level (e.g., M0 level), while the regular via will need to land on the wiring structure in an upper level (e.g., M1 or above level). Due to the skip via etching processes, though, damage will result at the interface between the wiring structure in the upper level and a via interconnect structure. That is, due to the different etch depths, the skip via etching process will result in surface damage to the upper wiring structure, e.g., copper material. This damage causes higher resistivity which, in turn, decreases device performance.
Also, in skip via processes, a conventional copper plating process is used to fill the vias. The copper plating process, though, grows from all directions including the sidewalls and bottom of the via resulting in extensive voids created due to pinch-off from sidewall growth and bottom voids from insufficient physical vapor deposition (PVD) seed coverage on the high aspect ratio via. Voids can also result from the undercut profile formed by ultra-low k (ULK) plasma-induced-damage (PID) or cap-to-interlevel dielectric selectivity. Also, the liner/seed is not sufficient to cover the full length of the high aspect ratio via, also resulting in void formation. These voids negatively affect the resistivity of the skip vias which, in turn, decreases device performance.